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d a t a sh eet preliminary speci?cation file under integrated circuits, ic02 1996 jan 17 integrated circuits TDA9144 i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator
1996 jan 17 2 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 features multi-standard colour decoder and sync processor for pal, ntsc and secam palplus helper demodulator palplus helper blanking and edtv-2 blanking i 2 c-bus controlled i 2 c-bus addresses hardware selectable pin compatible with tda9141 alignment free few external components designed for use with baseband delay lines integrated video filters adjustable luminance delay noise detector with i 2 c-bus read-out norm/no_norm detector with i 2 c-bus read-out cvbs or y/c input, with automatic detection possibility cvbs output provided i 2 c-bus address 8a is used vertical divider system two-level sandcastle signal va synchronization pulse (3-state) ha synchronization pulse or clamping pulse clp input/output line-locked clock output (6.75 mhz or 6.875 mhz) or stand-alone i 2 c-bus output port stand-alone i 2 c-bus input/output port colour matrix and fast yuv switch comb filter enable input/output with subcarrier frequency internal bypass mode of external delay line for palplus and ntsc applications low power standby mode with 3-state yuv outputs fast blanking detector with i 2 c-bus read-out blanked or unblanked sync on y out by i 2 c-bus bit bsy internal macrovision gating for the horizontal pll enabled by bus bit emg. general description the TDA9144 is an i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with helper demodulator for palplus signals and blanking facilities for palplus and edtv-2 signals. the TDA9144 has been designed for use with baseband chrominance delay lines, and has a combined subcarrier frequency/comb filter enable signal for communication with a pal/ntsc comb filter. the ic can process both cvbs input signals and y/c input signals. the input signal is available on an output pin, in the event of a y/c signal, it is added into a cvbs signal. the sync processor provides a two-level sandcastle, a horizontal pulse (clp or ha pulse, bus selectable) and a vertical (va) pulse. when the ha pulse is selected, a line-locked clock (llc) signal is available at the output port pin (6.75 mhz or 6.875 mhz). a fast switch can select either the internal y signal with the uv input signals, or yuv signals made of the rgb input signals. the rgb input signals can be clamped with either the internal or an external clamping signal. two pins with an input/output port and an output port of the i 2 c-bus are available. the i 2 c-bus address of the TDA9144 is hardware programmable. the TDA9144 is pin compatible with the tda9141 (multistandard decoder/sync processor). ordering information type number package name description version TDA9144 sdip32 plastic shrink dual in-line package; 32 leads (400 mil) sot232-1
1996 jan 17 3 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 quick reference data symbol parameter conditions min. typ. max. unit v cc positive supply voltage 7.2 8.0 8.8 v i cc supply current 50 60 70 ma v cvbs(p-p) cvbs input voltage (peak-to-peak value) top sync-white - 1.0 1.43 v v y(p-p) luminance input voltage (peak-to-peak value) top sync-white - 1.0 1.43 v v c(p-p) chrominance burst input voltage (peak-to-peak value) - 0.3 0.6 v v y(out) luminance black-white output voltage - 1.0 - v v y(out) luminance palplus output voltage black-white - 0.8 - v v y(out)(p-p) maximum luminance helper signal output voltage (peak-to-peak value) - 686 - mv v u(out)(p-p) u output voltage (peak-to-peak value) standard colour bar - 1.33 - v v v(out)(p-p) v output voltage (peak-to-peak value) standard colour bar - 1.05 - v v sc(bl) sandcastle blanking voltage level 2.2 2.5 2.8 v v sc(clamp) sandcastle clamping voltage level 4.2 4.5 4.8 v v va va output voltage 4.0 5.0 5.5 v v ha ha output voltage 4.0 5.0 5.5 v v llc(p-p) llc output voltage amplitude (peak-to-peak value) 250 500 - mv v r,g,b(p-p) rgb input voltage (peak-to-peak value) 0 to 100% saturation - 0.7 1.0 v v clamp(i/o) clamping pulse input/output voltage - 5.0 - v v sub(p-p) subcarrier output voltage amplitude (peak-to-peak value) 150 200 300 mv v oport port output voltage 4.0 5.0 5.5 v
1996 jan 17 4 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 block diagram handbook, full pagewidth mbg897 i 2 c-bus vertical sync separator sync separator matrix switch switch helper delay y clamp acc dgnd dec c y/cvbs o port/llc i/o port addr (cvbs) agnd cpll xtal xtal2 sda scl hpll sc clp/ha r g b f v cc filt ref fscomb va u out u in v in sec ref - (r - y) - (b - y) v out y out lca bias TDA9144 ina-inb horizontal pll secam cloche chroma bandpass trap ecl clp va ha ecl delay hue filter tuning secam demod fsc buffer ident system pal/ntsc demod chroma pll chroma switch timing generator tb bps ecmb yd3 - yd0 yh1 - yh0 18 14 13 12 3 4 2 6 22 15 16 26 25 8 927 28 29 30 31 23 1 32 2 57 24 11 17 21 20 19 10 2 fig.1 block diagram.
1996 jan 17 5 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 pinning symbol pin description - (r - y) 1 output signal for - (r - y) - (b - y) 2 output signal for - (b - y) u in 3 chrominance u input v in 4 chrominance v input scl 5 serial clock input sda 6 serial data input/output v cc 7 positive supply voltage dec 8 digital supply decoupling dgnd 9 digital ground sc 10 sandcastle output va 11 vertical acquisition synchronization pulse y out 12 luminance output v out 13 chrominance v output u out 14 chrominance u output i/o port 15 input/output port o port/llc 16 output port/line-locked clock output clp/ha 17 clamping pulse/ha synchronization pulse input/output f 18 fast switch select input b 19 blue input g 20 green input r 21 red input addr (cvbs) 22 i 2 c-bus address input (cvbs output) fscomb 23 comb ?lter status input/output hpll 24 horizontal pll ?lter c 25 chrominance input y/cvbs 26 luminance/cvbs input agnd 27 analog ground filt ref 28 ?lter reference decoupling cpll 29 colour pll ?lter xtal 30 reference crystal input xtal2 31 second crystal input sec ref 32 secam reference decoupling fig.2 pin configuration. handbook, halfpage TDA9144 mbg896 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - (b - y) - (r - y) u in v in scl sda v cc dec dgnd sc va y out v out u out sec ref xtal2 xtal cpll agnd y/cvbs filt ref c hpll fscomb addr (cvbs) r g b i/o port o port/llc f clp/ha
1996 jan 17 6 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 functional description the TDA9144 is an i 2 c-bus controlled, alignment-free pal/ntsc/secam colour decoder/sync processor which has been designed for use with baseband chrominance delay lines. for palplus signals, helper demodulation and blanking facilities are included; for edtv-2 (60 hz) signals only blanking facilities are included. in the standard operating mode the i 2 c-bus address is 8a. if the address input is connected to the positive supply rail the address will change to 8e. input switch the TDA9144 has a two pin input for cvbs or y/c signals which can be selected via the i 2 c-bus. the input selector also has a position in which it automatically detects whether a cvbs or y/c signal is on the input. in this input selector position, standard identification first takes place on an added y/cvbs and c input signal. after that, both chrominance signal input amplitudes are checked once and the input with the strongest chrominance burst signal is selected. the input switch status is read out by the i 2 c-bus via output bit yc. the auto input detect mode indicates yc = 1 for a vbs input signal (no chrominance component). cvbs output in the standard operating mode with i 2 c-bus address 8a, a cvbs output signal is available on the address pin, which represents either the cvbs input signal or the y/c input signal, added into a cvbs signal. rgb colour matrix the TDA9144 has a colour matrix to convert rgb input signals into yuv signals. a fast switch, controlled by the signal on pin f and enabled by i 2 c-bus via efs (enable fast switch), can select between these yuv signals and the yuv signals of the decoder. mode frgb = 1 (forced rgb) overrules efs and forces the matrixed rgb inputs to the yuv outputs. caution the voltage on the chrominance pin must never exceed 5.5 v. if it does, the ic enters a test mode. caution the voltage on the u in pin must never exceed 5.5 v. if it does, the ic enters a test mode. the y signal is internally connected to the switch. the - (r - y) and - (b - y) output signals of the decoder first have to be delayed in external baseband chrominance delay lines. the outputs of the delay lines must be connected to the uv input pins. if the rgb signals are not synchronous with the selected decoder input signal, clamping of the rgb input signals is possible by i 2 c-bus selection of ecl (external rgb clamp mode) and by feeding an external clamping signal to the clp pin. also in external rgb clamp mode the va output will be in a high impedance off-state. the yuv outputs can be put in 3-state mode by bus bit lps (low power standby mode). standard identi?cation the standards which the TDA9144 can decode depend upon the choice of external crystals. if a 4.4 mhz and a 3.6 mhz crystal are used then secam, pal 4.4/3.6 and ntsc 4.4/3.6 can be decoded. if two 3.6 mhz crystals are used then only pal 3.6 and ntsc 3.6 can be decoded. which 3.6 mhz standards can be decoded depends upon the exact frequencies of the 3.6 mhz crystals. in an application where not all standards are required only one crystal is sufficient; in this instance the crystal must be connected to the reference crystal input (pin 30). if a 4.4 mhz crystal is used it must always be connected to the reference crystal input. both crystals are used to provide a reference for the filters and the horizontal pll, however, only the reference crystal is used to provide a reference for the secam demodulator. to enable the calibrating circuits to be adjusted exactly, two bits from i 2 c-bus subaddress 00 are used to indicate which crystals are connected to the ic. the standard identification circuit is a digital circuit without external components. the search loop is illustrated in fig.3. the decoder (via the i 2 c-bus) can be forced to decode either secam or pal/ntsc (but not pal or ntsc). crystal selection can also be forced. information concerning standard and which crystal is selected and whether the colour killer is on or off is provided by the read out. using the forced-mode does not affect the search loop, it does however, prevent the decoder from reaching or staying in an unwanted state. the identification circuit skips impossible standards (e.g. secam when no 4.4 mhz crystal is fitted) and illegal standards (e.g. in forced mode). to reduce the risk of wrong identification pal has priority over secam. only line identification is used for secam. for a vertical frequency of 60 hz secam can be blocked to prevent wrong identification by means of bus bit saf.
1996 jan 17 7 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 fig.3 search loop of the identification circuit. handbook, full pagewidth pal killed pal killed pal killed ntsc killed ntsc killed secam killed reference crystal second crystal mge040 pal ntsc ntsc pal secam c c c c c c c c c c c integrated ?lters all chrominance bandpass and notch filters, including the luminance delay line, are an integral part of the ic. the filters are gyrator-capacitor type filters. the resonant frequency of the filters is controlled by a circuit that uses the active crystal to tune the secam cloche filter during the vertical flyback time. the remaining filters and the luminance delay line are matched to this filter. the filters can be switched to either 4.43 mhz, 4.29 mhz or 3.58 mhz. the switching is controlled by the standard identification circuit. the luminance notch used for secam has a lower q-factor than the notch used for pal/ntsc. the notches are provided with a little preshoot to obtain a symmetrical step response. in y/c mode the chrominance notch filters are bypassed, to preserve full signal bandwidth. for a cvbs signal the chrominance notch filters can be bypassed by bus selection of bit tb (trap bypass). the luminance to helper delay difference can be adjusted by i 2 c-bus, to achieve a correct fitting for the delay in the palplus helper demodulation signal path and the luminance path (not for helper only with trap). the delay of the colour difference signals - (r - y) and - (b - y) in the chrominance signal path and the external chrominance delay lines when used, can be fitted to the luminance signal delay control via i 2 c-bus in 40 ns steps. the typical luminance delay can be calculated: delay ? 90 + sak sbk {170 + 40( frq tb)} + 160(yd3) + 160(yd2) + 80(yd1) + 40(yd0) [ns].
1996 jan 17 8 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 colour decoder the pal/ntsc demodulator employs an oscillator that can operate with either crystal (3.6 mhz or 4.4 mhz). if the i 2 c-bus indicates that only one crystal is connected it will always connect to the crystal on the reference crystal input (pin 30). the hue signal which is adjustable by i 2 c-bus, is gated during the burst for ntsc signals. the secam demodulator is an auto-calibrating pll demodulator which has two references. the reference crystal, to force the pll to the desired free-running frequency and the bandgap reference, to obtain the correct absolute value of the output signal. the vco of the pll is calibrated during each vertical blanking period, when the ic is in search mode or secam mode. if the reference crystal is not 4.4 mhz the decoder will not produce the correct secam signals. especially for palplus and ntsc applications, an internal bypass mode of the external baseband delay line (for instance tda4665) is added, controlled by bus bit bps (bypass mode) and has a gain of 2. the bypass mode is not available for secam. comb ?lter interfacing the frequency of the active crystal is fed to the fscomb output, which can be connected to an external comb filter ic (e.g. saa4961). when bus bit ecmb is low, the subcarrier frequency is suppressed and its dc value is low. with ecmb high, the dc value is high with the subcarrier frequency present, and i 2 c-bus output bit yc and the input switch are always forced in the y/c mode, unless an external current sink (e.g. from the comb filter) prevents this, as pin fscomb also acts as input pin. in this event the subcarrier frequency is still present on the same dc high level pal plus helper demodulation palplus has been introduced to come to an evolutionary introduction of wide screen transmissions with backward compatibility with pal 4 : 3 tv sets. a palplus signal has the format of a standard analog pal composite signal containing 430 pal picture lines in letter box format (lines 60 to 274 and 372 to 586), together with helper information contained in the black bands above and below the visible letter box area (lines 24 to 59, 336 to 371, 275 to 310, and 587 to 622). a viewer with a 4 : 3 tv set will see a letter box picture: black bars of 1 8 picture height at the top as well as at the bottom with a 16 : 9 picture in between (see left-hand side picture of fig.4). a wide screen viewer without palplus decoder will only see the centre picture of fig.4, or the right hand side picture when a zoom option is available, however with only 430 lines of vertical resolution. when a wide screen viewer has a palplus decoder, it expands the letter box format to a full-size wide screen picture with a vertical resolution of 574 lines. the decoder uses the helper lines information, hidden within the black bars. see the right-hand side picture of fig.4. furthermore a palplus signal will deliver full luminance bandwidth by an y/c separation technique called motion adaptive colour plus (macp). using this technique, the signal becomes free from cross colour and cross luminance. this algorithm requires macp pre-processing in the palplus encoder at the studio output. the palplus parts which the TDA9144 processes are in short: helper demodulation and multiplexing helper with letter box luminance signal chrominance trap bypassing if necessary creation of reference line 22 (see fig.5) creation of black set-up and helper set-up correct blanking and timing reference for the necessary post processing ics. fig.4 possible palplus picture displays. handbook, full pagewidth 430 picture lines 574 picture lines helper lines helper lines mbg903
1996 jan 17 9 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 in case of a palplus input signal, the standard identification system of the TDA9144 only determines pal and needs additional i 2 c-bus information for palplus, via bus bits macp, hd, hob and hbc. bus bit macp determines whether the 4.43 chrominance signal component of the cvbs input signal should be suppressed by a 4.43 trap or not. for macp = 1 the chrominance suppression takes place outside the TDA9144. the hd bit (helper demodulation) enables palplus helper demodulation on the u phase (i.e. the b - y demodulation axis). as there is only a 4.43 notch for the demodulated helper, an external notch filter is necessary to suppress the 8.86 mhz demodulation product and resolve the baseband helper signal. the demodulated helper luminance signal is always led to a notch filter (4.43 mhz, no bypass here), then multiplexed with the regular 430 letter box lines luminance signal and led to the output y out . the black level of the luminance signal is internally clamped with a large time constant to the black level generated by the helper demodulator. also bus bits hd and macp determine the presence of a black set-up voltage (with luminance scaling of a factor 0.8) and a helper set-up voltage for the demodulated helper signal on the output signal y out . these set-up voltages are necessary for palplus signal post processing outside the TDA9144. the set-up voltages are also multiplexed into a reference line 22, combined with the demodulated helper reference of line 23 and luminance reference of line 623, both present in every palplus signal for correct palplus reference post processing (see fig.5). additional helper blanking bits (hob, hbc) determine whether the helper signal has to be blanked or blanked conditionally depending on the signal-to-noise ratio bit snr. helper blanking can only take place on a norm sync signal, indicated by output bit nrm = 1. table 1 is valid in 50 hz or 60 hz mode. table 1 helper blanking modes for edtv-2 (system m, 60 hz, 525 lines) outside the letter box area, blanking is possible and takes place on lines hob hbc snr helper blanking 0 x x off 10xon 110off 111on 230 to 312 and 493 to 49 (1) when helper blanking is activated. the TDA9144 can handle palplus signals in either cvbs or y/c format. in case of a y/c signal, the modulated helper must be available on the chrominance input pin (c). the use of the 4.43 trap will not be necessary, as the chrominance and luminance components of a y/c signal are already separated, so the 4.43 trap for the letter box luminance is bypassed (not for the demodulated helper signal). during helper demodulation, the internal chroma bandpass filter is bypassed. for palplus the i 2 c-bus hue bits hu0 to hu5 are used to adjust for a correct helper demodulator phase. this has no effect on the r - y and b - y demodulator phase for pal. table 2 gives an overview of the possible palplus modes and their effects in the TDA9144. the table is only valid for a 50 hz system. in 60 hz system mode the columns for line 22, 23b and 623a do not exist, and using the macp and hd bits has no effect on the 60 hz signal. mode 1 ? normal pal mode 2 ? pal with macp processing mode 3 ? full palplus mode 4 ? palplus without macp processing (helper only) mode 5 ? near_norm or no_norm sync condition mode 6 ? norm sync condition with fast blanking active mode 7 ? system ident not identified as pal. the indications a and b for the lines 22, 23 and 623 respectively stand for the first half and the second half of a line. the signalling bits in line 23 (see fig.5) are processed in the same manner as letter box luminance lines in the TDA9144. signalling bit decoding and palplus identification is done externally with i 2 c-bus as communication link to the TDA9144 for bus bits macp, hd, hob, and hbc. (1) for system m the line numbers start with the ?rst equalizing pulse in ?eld 1, but the internal line counter starts counting at the ?rst vertical sync pulse in ?eld 1. this line number notation is used here and in fig.9.
1996 jan 17 10 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 handbook, full pagewidth 1.00 0.30 0 20 m s 32 m s line 623 (v) palplus cvbs in 10 m s 10.5 m s white level reference 1.00 0.30 0 (v) ebu colour bar ebu colour bar with black set-up 1.00 0.60 0.20 0 (2) (v) 1.00 0.30 0.45 0.80 0.15 0 (v) line 23 input signals output signals 41 m s 51 m s 0.4 m s 10.83 m s palplus signalling bits black level reference helper reference burst - u phase 1.00 0.60 0.77 0.20 0 (v) line 23 helper set-up b palplus signalling bits 1.00 0.20 0.60 0 (v) 52 m s 0.15 m s 0.4 m s 686 mv 0.65 m s 52 m s 22 m s 30.8 m s 0.15 m s 0.65 m s baseband helper line with black and helper set-up 1.00 0.30 0.45 0.15 0 (v) 52 m s 10.5 m s max. modulated helper line demodulated helper area limits 800 mv delay clp to set up (4) demodulated helper reference 1.00 0.60 0.20 0 (v) line 22 reference line helper set-up (mid-grey) black set-up 212 llc pulses 151 llc pulses a 11.2 m s 1.00 0.60 0.20 0 (v) line 623 black set-up black (clamp level) black level offset y out (pin 12) y black white level reference (1) mid-grey offset = a - b (3) mbg904 fig.5 palplus cvbs input and y output signals. figures drawn when using subaddress 8a and an y delay of ~ 440 ns. llc frequency equals 6.875 mhz; 440 llc pulses per horizontal line. demodulated helper shown when using an external 8.8 notch filter. (1) see y output parameter v os in section characteristics (2) see demodulated helper parameter t d in section characteristics (3) see demodulated helper parameter v os in section characteristics (4) see clp output/ha output parameter t d in section characteristics
1996 jan 17 11 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 table 2 palplus modes for 50 hz notes 1. when activated, the black set-up is added to the full frame. 2. when activated, the helper set-up is added to line 22b, 23b, 24 to 59, 275 to 310, 336 to 371, 587 to 622. 3. the 4.43 mhz trap is active in cvbs input mode and tb = 0, otherwise the trap is bypassed. 4. when helper blanking is active (see table 1) lines 24 to 59, 275 to 310, 336 to 371, 587 to 622 are blanked. 5. demodulated helper with 400 mv set-up and 4.43 mhz trap active. 6. the 4.43 mhz trap is bypassed during the letter box lines, but activated during helper lines and line 23b to reduce 4.43 mhz res t carrier. 7. the 4.43 mhz trap is active during helper lines and line 23b, during the letter box lines the trap is active when tb = 0. 8. in principle the comb filter should be enabled during letter box lines, when ecmb = 1. it depends on the comb filter if this wi ll be implemented. 9. line 623a contains luminance in no_norm, line 623a is black in a near_norm sync condition. mode macp hd nrm fba pal 4.43 trap comb enable delay line luma ampl (b-w) (v) black set-up (1) (mv) helper set-up (2) (mv) helper lines line 22 line 23b line 623a 100101tb (3) ecmb bps 1 0 0 luma (4) black black black 2 1 0 1 0 1 bypass disabled bps 0.8 200 0 luma (4) set-up helper (5) luma 3 1 1 1 0 1 bypass (6) disabled bypass 0.8 200 400 helper (4) set-up helper luma 401101tb (7) disabled (8) bypass 0.8 200 400 helper (4) set-up helper luma 5xx0xxtb (3) ecmb bps 1 0 0 luma black black luma (9) 6xx11xtb (3) ecmb bps 1 0 0 luma (4) black black black 7xx1x0tb (3) ecmb bps 1 0 0 luma (4) black black black
1996 jan 17 12 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 fast blanking detector for palplus it is necessary to switch-off palplus as soon as an external rgb input signal is mixed into a palplus signal via a switching signal on the fast blanking input (f). to detect the presence of a fast blanking signal, a circuit is added which forces the macp and hd bit to zero if in more than one line per field a blanking pulse is detected. more than one line per field is chosen to prevent switching-off at every spike detected on the fast blanking input. the detector output fba (fast blanking active) can be read-out by the i 2 c-bus. blanked/unblanked sync by means of the i 2 c-bus bit bsy (blanked sync), output signal y out will be presented with or without its composite sync part. at bsy = 0 the composite sync is present on y out . when activated, helper blanking takes place only during helper lines scan. at bsy = 1 the black level is filled in during the line blanking interval and vertical blanking interval. when activated, the helper blanking extends the vertical blanking. for palplus modes with black set-up no composite sync will be present on y out , independent of the bsy condition. sync processor ( j 1 loop) the main part of the sync circuit is an oscillator running at 440 f h (6.875 mhz), provided that i 2 c-bus address 8a is used or 432 f h (6.75 mhz) for 8e. its frequency is divided by 440 or 432 to lock the j 1 loop to the incoming signal. the time-constant of the loop can be selected by the i 2 c-bus (fast, auto or slow). in the fast mode the fast time-constant is chosen independent of signal conditions. in auto mode the medium time-constant is present with a fast time constant during the vertical retrace period ('field boost'). if the noise detector indicates a noisy video signal the time-constant switches to slow with a smaller field boost, which is also the time-constant for the slow mode. in case of a slow time constant sync gating takes place in a 6 m s window around the separated sync pulse. in case of no sync lock, both the auto and the slow mode have a medium time constant, to ensure reliable catching. the noise content of the video signal is determined by a noise detector circuit. this circuit measures the noise at top sync during a 15 line period every field (65 lines after start va pulse). when the noise level supersedes the detector threshold in two consecutive fields, noise is indicated and bus bit snr is set. the free-running frequency of the oscillator is determined by a digital control circuit that is locked to the active crystal. when a power-on-reset pulse is detected the frequency of the oscillator is switched to a frequency of about 10 mhz (23 khz horizontal frequency) to protect the horizontal output transistor. the oscillator frequency is calibrated to 6.875 mhz or 6.75 mhz after receiving data on subaddress 01 for the first time after power-on-reset detection. to ensure that this procedure does not fail it is absolutely necessary to send subaddress 00 before subaddress 01. subaddress 00 contains the crystal indication bits and when subaddress 01 is received the line oscillator calibration will be initiated (for the start-up procedure after power-on-reset detection, see the i 2 c-bus protocol). the calibration is terminated when the oscillator frequency reaches 6.875 mhz or 6.75 mhz. the j 1 loop can be opened using the i 2 c-bus. this is to facilitate on screen display (osd) information. if there is no input signal or a very noisy input signal, the j 1 loop can be opened to provide a stable line frequency, and thus a stable picture. the sync part also delivers a two-level sandcastle signal, which provides a combined horizontal and vertical blanking signal and a clamping pulse for the display section of the tv. macrovision sync gating a dedicated gating signal for the separated sync pulses, starting 11 lines after the detection of a vertical sync pulse until picture scan starts, can be used to improve the behaviour of the horizontal pll with respect to the unwanted disturbances caused by the pseudo-sync pulses in video signals with macrovision anti-copy guard signals. this sync gating excludes the pseudo-sync pulses and can only take place in the auto and fast j 1 time constant mode, provided i 2 c-bus bit snr = 0 and i 2 c-bus
1996 jan 17 13 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 bit emg = 1. i 2 c-bus bit emg = 1 enables and emg = 0 disables this sync gating in the horizontal pll. vertical divider system the vertical divider system has a fully integrated vertical sync separator. the divider can accommodate both 50 hz and 60 hz systems; it can either determine the field frequency automatically or it can be forced to the desired system via the i 2 c-bus. a block diagram of the vertical divider system is illustrated in fig.6. the divider system operates at twice the horizontal frequency. the line counter receives enable pulses at this frequency, thereby counting two pulses per line. a state diagram of the controller is shown in fig.7. because it is symmetrical only the right-hand part will be described. depending on the previously found vertical frequency, the controller will be in one of the count states. when the line counter has counted 488 pulses (i.e. 244 lines of the video input signal), the controller will move to the next state depending on the output of the norm counter. this can be either norm, near_norm or no_norm, depending on the position of the vertical sync pulse in the previous fields. when the controller is in the norm state it generates the vertical sync pulse (vsp) automatically and then, when the line counter is at lc = 626, moves to the wait state. in this condition it waits for the next pulse of the double line frequency signal, and then moves to the count state of the current field frequency. fig.6 block diagram of the vertical divider system. handbook, halfpage mge043 norm counter controller timing generator line counter when the controller returns to the count state, the line counter will be reset half a line after the start of the vertical sync pulse of the video input signal. the norm window normally looks within one line width and a sudden half line delay of the vertical sync pulse change can therefore be neglected, but for palplus conditions every half line shift of the vertical sync pulse must be detected. in this case a half line window is used. when the controller is in the near_norm state it will move to the count state if it detects the vertical sync pulse within the near_norm window (i.e. 622 < lc < 628). if no vertical sync pulse is detected the controller will move back to the count state when the line counter reaches lc = 628. the line counter will then be reset. when the controller is in the no_norm state, it will move to the count state when it detects a vertical sync pulse and reset the line counter. if a vertical sync pulse is not detected before lc = 722 (if the j 1 loop is locked, even in forced mode) it will move to the count state and reset the line counter. if the j 1 loop is not locked the controller will return to the count state when lc = 628. the forced mode option keeps the controller in either the left-hand side (60 hz) or the right-hand side (50 hz) of the state diagram. figure 8 illustrates the state diagram of the norm counter which is an up/down counter that increases its counter value by 1 if it finds a vertical sync pulse within the selected window. if not it decreases the counter value by 1 (or 2, see fig.8). in the near_norm and norm states the first correct vertical sync pulse after one or more incorrect vertical sync pulses is processed as an incorrect pulse. this procedure prevents the system from staying in the near_norm or norm state if the vertical sync pulse is correct in the first field and incorrect in the second field. in case of no sync lock (sln = 1) the norm counter is reset to no_norm (wide search window), for fast vertical catching when switching between video sources. fast switching between different channels however can still result in a continuous horizontal sync lock situation, when the channel is changed before the norm counter has reached the norm state. to provide faster vertical catching in this case, measures have been taken to prevent the norm counter to count down to zero before reaching the no_norm state (see left-hand of fig.8). bus bit fww (forced wide window) enables the norm counter to stay in the no_norm state if desired. the norm/no_norm status is read out by bus bit nrm.
1996 jan 17 14 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 fig.7 state diagram of the vertical divider system. handbook, full pagewidth mge042 wait for reset pulse no norm norm norm count count lc = 528 or lc = 576 or on vsp lc = 628 or lc = 722 or on vsp no_norm else no_norm norm norm lc < 488 lc 525 lc 625 near norm near norm lc < 522 lc < 622 lc < 488 on sync if lc < 576 on sync if lc 3 576 lc = 526 lc = 626 on vsp if 522 < lc < 528 or on lc = 528 on vsp if 622 < lc < 628 or on lc = 628 vertical frequency 60 hz vertical frequency 50 hz near_norm near_norm
1996 jan 17 15 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 fig.8 state diagram of the norm counter. (1) vsp found: count 1 up; no vsp found: count 2 down. handbook, full pagewidth mge041 norm no norm near norm near norm near norm 22 < nc 27 0 nc < 12 10 < nc < 26 (1) 10 < nc < 17 0 < nc < 14 nc = 26 nc = 17 nc = 14 nc = 10 (reset nc) nc = 10 (reset nc) nc = 22 nc = 0 nc = 12 (reset nc) norm test area near_norm test area
1996 jan 17 16 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 output port and in/output port two stand-alone ports are available for external use. these ports are i 2 c-bus controlled, the output port by bus bit opb and the input/output port by bus bit opa. bus bit opa is an open-drain output, to enable input port functionality. the pin status is read out by bus via output bit ip. sandcastle figure 9 illustrates the timing of the acquisition sandcastle (asc) and the va pulse with respect to the input signal. the sandcastle signal is according to the two-level 5 v sandcastle format. an external vertical guard current can overrule the sink current to enable blanking purposes. handbook, full pagewidth mbg902 asc va asc asc va asc 23 625 312 (1) 262 525 17 280 50 hz 60 hz 2nd field 1st field 336 2nd field 1st field 2nd field 1st field 2nd field 1st field fig.9 acquisition sandcastle signal and va pulse timing diagram. (1) see vertical section in characteristics
1996 jan 17 17 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 i 2 c-bus for address 8a, an unconnected pin 22 is sufficient as this pin is also a cvbs output. do not short-circuit the input to ground. if the address input is connected to the positive supply rail, the address changes from 8a to 8e. table 3 slave address (8a) valid subaddresses: 00 to 03 and 17 to 18 (hex). only the five least significant bits of the subaddress bytes are recognized. auto-increment mode available for subaddresses. the output addresses 00 and 01 can only be read in auto-increment mode. the i 2 c-bus transceiver is designed for a maximum clock frequency (f scl ) of 100 khz. table 4 input bytes table 5 output (status) bytes start up procedure: read the status byte until por = 0; send subaddress 18 with the lps bit indicating normal operation (lps = 0); send subaddress 00 with the crystal indicator bits (xa and xb) indicating that only one crystal is connected to the ic (1) ; wait for 50 ms; send subaddress 01; wait for at least 50 ms; set xa,xb to the actual crystal configuration. each time before the data in the ic is refreshed, the status byte must be read. if por = 1, then the above procedure must be carried out to restart the ic. as long as por = 1, sending subaddress 01 does not start the line oscillator calibration. por is reset when the status register is read out and can only be reset when the supply voltages exceed the por detection levels mentioned in the bias generator characteristics (see chapter characteristics). failure to stick to the above procedure may result in an incorrect horizontal frequency after power-up or a power-dip. remark: if the presence of output signals ha/clp and/or va is required after power-up of the ic, subaddress 02 with the ecl bit indicating ecl = 0 must be sent before sending subaddress 00. (1) to be absolutely sure that the line oscillator is calibrated with the appropriate crystal frequency data, it is possible to check the received values of the crystal indication bits via status bits sxa and sxb. slave address a6 a5 a4 a3 a2 a1 a0 r/ w 8a 10001x1x sub address msb data byte lsb d7 d6 d5 d4 d3 d2 d1 d0 00 ina inb tb ecmb foa fob xa xb 01 forf fors opa opb poc fm saf frqf 02 efs ecl hu5 hu4 hu3 hu2 hu1 hu0 03 lca fww ------ ......... 17 macp hd hob hbc bsy yh2 yh1 - 18 bps lps frgb emg yd3 yd2 yd1 yd0 output address d7 d6 d5 d4 d3 d2 d1 d0 00 por fsi yc sl ip sak sbk frq 01 --- fba nrm snr sxa sxb
1996 jan 17 18 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 input signals table 6 source select; note 1 note 1. when ecmb = 1 and no current is drawn from the fscomb pin, source select is forced to be yc. table 7 trap bypass; note 1 note 1. the chrominance trap is always bypassed in yc mode or when macp = 1. table 8 comb ?lter enable; note 1 note 1. macp = 1 or hd = 1 always enforces ecmb = 0. table 9 j 1 time constant table 10 crystal indication ina inb source 0 0 cvbs 01yc 1 - auto cvbs / yc tb condition 0 trap not bypassed 1 trap bypassed ecmb condition 0 comb ?lter disabled 1 comb ?lter enabled foa fob mode 0 0 auto 0 1 slow 1 - fast xa xb crystal 002 3.6 mhz 011 3.6 mhz 101 4.4 mhz 111 3.6 mhz and 1 4.4 mhz table 11 forced ?eld frequency table 12 output value i/o port table 13 output value o port table 14 j 1 loop control table 15 forced standard; note 1 note 1. if xa and xb indicate that only one crystal is connected to the ic and fm and frqf force it to use the second crystal, then colour will be switched off. when saf = 0, secam 60 hz is disabled; when saf = 1, secam 60 hz is enabled. table 16 enable fast switch forf fors field frequency 0 0 auto; 60 hz if no lock 0 1 60 hz 1 0 50 hz 1 1 auto; 50 hz if no lock opa level 0 low 1 high opb level 0 low 1 high poc condition 0 j 1 loop closed 1 j 1 loop open fm saf frqf standard 0 -- auto search 1 0 0 pal/ntsc second crystal 1 0 1 pal/ntsc reference crystal 1 1 0 black and white 1 1 1 secam reference crystal efs condition 0 fast switch disabled 1 fast switch enabled, when frgb = 0
1996 jan 17 19 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 table 17 external rgb clamp mode table 18 forced rgb mode table 19 yuv outputs as a function of efs, frgb and fast switch f table 20 hue table 21 line-locked clock active table 22 forced wide window table 23 motion adaptive colour plus; note 1 note 1. black set-up will only be present in a norm sync condition. ecl condition 0 off; internal clamp pulse is used 1 on; external clamp pulse has to be supplied to clp pin frgb condition 0 yuv, when disabled via efs 1 forced rgb efs frgb f selected inputs 00 - yuv - 1 - rgb 100yuv 101rgb function address digital number hue hu5 to hu0 000000 = - 45 111111 = +45 lca condition 0 opb/clp mode 1 llc/ha mode fww condition 0 auto window mode 1 forced wide window macp condition 0 internal 4.43 notch used 1 external macp chrominance ?ltering used, 4.43 notch bypassed, black set-up 200 mv table 24 palplus helper demodulator active; note 1 note 1. black set-up and helper set-up will only be present in a norm sync condition. table 25 palplus/edtv-2 helper blanking (y, u, v) table 26 blanked sync on y out note 1. except for palplus with black set-up. table 27 luminance to helper delay control table 28 baseband delay line bypass; note 1 note 1. when hd = 1 the baseband delay line is forced into bypass mode. secam cannot be bypassed. table 29 low power standby mode hd condition 0off 1 on, palplus mode with helper set-up 400 mv and black set-up 200 mv hob hbc snr blanking 0 -- off 10 - on 110 off 111 on bsy condition 0 unblanked sync; note 1 1 blanked sync yh2 to yh1 condition 00 - 20 ns 11 +25 ns bps condition 0 no bypass 1 baseband delay line bypassed lps condition 0 normal operation 1 low power standby
1996 jan 17 20 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 table 30 enable macrovision gating table 31 luminance delay control output signals table 32 power-on reset table 33 field frequency indication table 34 input switch mode table 35 j 1 lock indication table 36 input value i/o port emg condition 0 disable gating 1 enable gating yd3 to yd0 condition 0000 - 280 ns 1111 +160 ns por condition 0 normal mode 1 power-down mode fsi condition 050hz 160hz yc condition 0 cvbs mode 1 y/c mode sl condition 0 not locked 1 locked ip level 0 low 1 high table 37 standard read-out table 38 fast blanking active table 39 norm/no_norm indication in vertical divider system table 40 signal-to-noise ratio table 41 crystal indication read-out sak sbk frq standard 0 0 0 pal second crystal 0 0 1 pal reference crystal 0 1 0 ntsc second crystal 0 1 1 ntsc reference crystal 1 0 0 illegal forced mode 1 0 1 secam reference crystal 11 - colour off fba condition 0 no fast blanking detected 1 fast blanking detected nrm condition 0 no_norm or near_norm 1 norm snr condition 0 s/n > 20 db 1 s/n < 20 db sxa sxb crystal 002 3.6 mhz 011 3.6 mhz 101 4.4 mhz 111 3.6 mhz and 1 4.4 mhz
1996 jan 17 21 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 limiting values in accordance with the absolute maximum rating system (iec 134). thermal characteristics quality specification quality level in accordance with snw-fq-611-e is applicable for esd protection, human body model: 3000 v, 100 pf, 1500 w on all pins. machine model: 300 v, 200 pf, 0 w on all pins. the number of the quality specification can be found in the quality reference handbook . the handbook can be ordered using the code 9397 750 00192. symbol parameter conditions min. typ. max. unit v cc supply voltage -- 9.0 v i cc supply current -- 70 ma p tot total power dissipation -- 630 mw t stg storage temperature - 55 - +150 c t amb operating ambient temperature - 10 - +70 c symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air 48 k/w
1996 jan 17 22 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 characteristics v cc =8v; t amb =25 c; i 2 c-bus address 8a; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply (pin 7) v cc supply voltage 7.2 8.0 8.8 v i cc supply current 50 60 70 ma p tot total power dissipation 360 480 620 mw i cc low power supply current 12 16 22 ma input switch caution: the voltage on pin 25 must never exceed 5.5 v, if it does, the ic enters a test mode y/cvbs input ( pin 26) v i(p-p) input voltage (peak-to-peak value) top sync-white - 1.0 1.43 v z i input impedance 60 -- k w c i input capacitance -- 5pf i i(bias) input bias current - 3.3 -m a c input ( pin 25) v i(p-p) input burst voltage (peak-to-peak value) - 0.3 0.6 v z i input impedance 60 -- k w c i input capacitance -- 5pf cvbs output ( pin 22); only for address 8a v o(p-p) output voltage (peak-to-peak value) top sync-white - 1.0 - v z o output impedance -- 500 w b bandwidth at - 3db c l =15pf 7 -- mhz v tsl top-sync voltage level 2.2 2.8 3.4 v bias generator (pin 8) v d(dec) digital supply voltage 4.8 5.0 5.2 v v det(cc) por detection level for power supply 5.7 6.0 6.3 v v det(dec) por detection level for dec pin 4.0 4.3 4.6 v i l(dec) current load on digital supply sum of pins 8, 11, 16, 17 -- 2.0 ma subcarrier regeneration g eneral ; note 1 cr catching and holding range reference crystal 500 -- hz second crystal 450 -- hz j phase shift for 80% deviation of catching range -- 5 deg z i input impedance reference crystal and second crystal 0.80 1.00 1.20 k w
1996 jan 17 23 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 f scomb output ( pin 23) v sub(p-p) subcarrier output voltage amplitude (peak-to-peak value) c l = 15 pf 150 200 300 mv v cen comb enable voltage level 4.0 4.2 5.0 v v cdis comb disable voltage level - 0.1 1.4 v i sink sink current to undo forced y/c mode of input switch 0.4 - 1.0 ma r gnd value of grounded resistor to undo forced y/c mode of input switch 4 - 10 k w acc acc control range - 20 - +6 db change of - (r - y) and - (b - y) signals over range -- 1db colour killer treshold pal/ntsc - 34 - 31 - 28 db secam - 31 - 28 - 25 db kill/unkill hysteresis - 3 - db demodulators; - (r - y) and - (b - y) outputs (pins 1 and 2); demodulated y helper (pin 12) g eneral ratio of - (b - y) to - (r - y) standard colour bar 1.20 1.27 1.34 tc temperature coef?cient of - (r - y) and - (b - y) amplitude -- 0.1 %/k spread of - (r - y) to - (b - y) ratio between standards - 1 - +1 db v - (r - y) output level of - (r - y) output during blanking level 1.7 2.1 2.5 v v - (b - y) output level of - (b - y) output during blanking level 1.7 2.0 2.5 v b bandwidth at - 3 db 600 670 750 khz z o output impedance -- 500 w d v cc supply voltage dependence -- 2 %/v j hue phase shift note 3 35 45 55 deg pal/ntsc demodulator v - (r - y)(p-p) - (r - y) output voltage (peak-to-peak value) standard colour bar 480 540 605 mv v - (b - y)(p-p) - (b - y) output voltage (peak-to-peak value) standard colour bar 610 685 765 mv v res(p-p) 8.8 mhz residue (peak-to-peak value) both outputs -- 15 mv v res(p-p) 7.2 mhz residue (peak-to-peak value) both outputs -- 20 mv v res(p-p) 4.4 and 3.6 mhz residue both outputs -- tbf mv s/n signal-to-noise ratio 0 to 1 mhz 46 -- db symbol parameter conditions min. typ. max. unit
1996 jan 17 24 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 pal demodulator v r(p-p) 1 2 h ripple (peak-to-peak value) -- 20 mv j demodulator phase error -- 5 deg secam demodulator v - (r - y)(p-p) - (r - y) output voltage (peak-to-peak value) standard colour bar 0.96 1.08 1.21 v v - (b - y)(p-p) - (b - y) output voltage (peak-to-peak value) standard colour bar 1.22 1.37 1.53 v f os black level offset frequency -- 7 khz s/n signal-to-noise ratio 0 to 1 mhz 40 -- db v res(p-p) 7.8 mhz to 9.4 mhz residue (peak-to-peak value) -- 30 mv f pole pole frequency of de-emphasis 77 85 93 khz ratio of pole and zero frequency - 3 - v cal calibration voltage 345v nl non linearity -- 3% d emodulated helper ( pin 12) v y(p-p) helper output voltage (peak-to-peak value) palplus limits 610 686 770 mv v y(p-p) helper set-up amplitude only helper lines, line 22 and line 23 380 400 420 mv t d group delay within passband -- 10 ns j demodulator phase including 1 2 h error -- 5 deg a c(m/d) crosstalk modulated helper to demodulated sign 0 to 1 mhz - 36 -- db 4.43 mhz residue - 36 -- db thd total harmonic distortion in acc - 36 -- db t y helper output timing to y out -- 10 ns v os offset demodulator mid-grey to inserted mid-grey level mid-grey line 23 and line 22; see fig.5 -- 5mv t su helper set-up width (363 llc pulses) and start helper set-up - 52.8 -m s t d delay between mid-sync of input and start helper set-up yd3 to yd0 = 1011; note 4; see fig.5 - 8.8 -m s t d delay between start black set-up and start helper set-up (212 llc pulses) only line 22 and 23 - 30.8 -m s b baseband helper bandwidth at - 3db - 2.6 - mhz filters t uning v tune tuning voltage 1.5 3 6 v symbol parameter conditions min. typ. max. unit
1996 jan 17 25 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 l uminance delay ; yd3 to yd0 = 1011; yh2 to yh1 = 01 t d(on) delay time colour on f sc = 3.6 mhz; tb = 0 555 580 605 ns f sc = 3.6 mhz and 4.4 mhz; tb = 1 515 540 565 ns t d(off) delay time colour off 350 370 390 ns t d(tun) delay time tuning range 15 steps yd3 to yd0; note 2 - 280 - +160 ns t d(tun) y to helper delay tuning range 3 steps yh2 to yh1 - 20 - +25 ns c hrominance trap f o notch frequency f sc = 3.6 mhz 3.53 3.58 3.63 mhz f sc = 4.4 mhz 4.37 4.43 4.49 mhz secam 4.23 4.29 4.35 mhz y/c and b/w mode not active b bandwidth at - 3db f sc = 3.6 mhz 2.60 2.80 3.00 mhz f sc = 4.4 mhz 3.20 3.50 3.80 mhz secam 2.90 3.15 3.50 mhz f sc(sup) subcarrier suppression 26 -- db c hrominance bandpass f res resonant frequency f sc = 3.6 mhz 3.40 3.58 3.76 mhz f sc = 4.4 mhz 4.21 4.43 4.65 mhz b bandwidth at - 3db f sc = 3.6 mhz 1.05 1.20 1.35 mhz f sc = 4.4 mhz 1.25 1.40 1.55 mhz c loche filter f res resonant frequency secam 4.26 4.29 4.31 mhz b bandwidth at - 3 db secam 241 268 295 khz sync input (pin 26) v ideo input v y/cvbs(p-p) sync pulse amplitude (peak-to-peak value) 35 300 600 mv slicing level 40 47 55 % t d delay of sync pulse due to internal ?lter 0.2 0.3 0.4 m s n th noise detector threshold level 18 20 22 db h hysteresis 235db t d delay between internally separated vertical sync pulse and video signal 12 18.5 27 m s symbol parameter conditions min. typ. max. unit
1996 jan 17 26 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 horizontal section clp output (opb/clp mode ); ha output (llc/ha) mode ( both on pin 17) v oh high level output voltage 4.0 5 5.5 v v ol low level output voltage - 0.2 0.4 v i sink sink current 2 -- ma i source source current 2 -- ma t w(ha) ha pulse width (32 llc pulses) - 4.65 -m s t d delay between middle of horizontal sync pulse and middle of h a note 4 0.3 0.45 0.6 m s t w clp pulse width (25 llc pulses) - 3.65 -m s t d delay start clp pulse to start black set-up (33 llc pulses + y delay) hd = 1 or macp = 1; yd3 to yd0 = 1011; see fig.5 - 5.35 -m s t d delay between middle of horizontal sync pulse and start of clp pulse note 4 3.0 3.2 3.4 m s s 6 s jitter j 1 in auto mode -- 5ns f irst loop ( j 1 ) d f frequency deviation when not locked -- 1.5 % d v cc supply voltage dependence - 40 - hz/v f cr catching range 625 -- hz f hr holding range -- 1.0 khz f static phase shift -- 0.1 m s/khz llc output ( pin 16); llc/ha mode f o output frequency 440 f h 50 hz standard - 6.875 - mhz 440 f h 60 hz standard - 6.923 - mhz v o(p-p) output amplitude (peak-to-peak value) 0.25 -- v v o dc output voltage level - 2.5 v t d delay between negative edge of llc and positive edge of ha pulse c l =15pf 102040ns vertical section v ertical oscillator f fr free running frequency forf = 1; divider ratio 628 - 50 - hz forf = 0; divider ratio 528 - 60 - hz f lr frequency locking range 43 - 64 hz lr divider locking range 488 625 722 symbol parameter conditions min. typ. max. unit
1996 jan 17 27 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 va output ( pin 11); ecl = 0 v oh high level output voltage 4.0 5 5.5 v v ol low level output voltage - 0.2 0.4 v i sink sink current 2 -- ma i source source current 2 -- ma t w(va) v a pulse width 2.5/f h 50 hz standard - 160 -m s 3/f h 60 hz standard - 192 -m s t d delay between start of vertical sync pulse and positive edge of va note 5; see fig.9 - 35 -m s z o output impedance ecl = 1 3 -- m w sandcastle output (pin 10) v o zero level output voltage 0 0.5 1 v i sink sink current 0.5 0.7 0.9 ma h orizontal and vertical blanking v bl blanking voltage level 2.2 2.5 2.8 v i source source current 0.5 0.7 0.9 ma i ext external current required to force the output to the blanking level 1.0 - 3.0 ma t w(h) horizontal blanking pulse width (69 llc pulses) - 10.0 -m s t d delay between start of horizontal blanking and start of clamping pulse (44 llc pulses) - 6.4 -m s c lamping pulse v clamp clamping voltage level 4.2 4.5 4.8 v i source source current 0.5 0.7 0.9 ma t w(clamp) clamping pulse width (25 llc pulses) - 3.6 -m s t d delay between middle sync of input and start of clamping pulse note 4 3.0 3.2 3.4 m s yuv/rgb switches caution: the voltage on pin 3 must never exceed 5.5 v, if it does, the ic enters a test mode rgb inputs ( pins 21, 20 and 19 respectively ); note 6 v i(p-p) input voltage (peak-to-peak value) - 0.7 1 v z i input impedance 3 -- m w c i input capacitance -- 5pf uv inputs ( pins 3 and 4 respectively ); note 6 v i(p-p) u input voltage (peak-to-peak value) - 1.33 1.90 v v i(p-p) v input voltage (peak-to-peak value) - 1.05 1.50 v z i input impedance (both inputs) 3 -- m w c i input capacitance (both inputs) -- 5pf symbol parameter conditions min. typ. max. unit
1996 jan 17 28 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 y output ( pin 12) v o(p-p) u output voltage black-white - 1.00 - v v o(p-p) palplus output voltage black-white - 0.80 - v z o output impedance -- 250 w v o dc output voltage level black level 2.7 3.0 3.3 v s/n signal-to-noise ratio f = 0 to 5 mhz - 52 - db v out black set-up amplitude macp = 1 or hd = 1 190 200 210 mv t w(black) black set-up width 363 llc pulses - 52.8 -m s t d delay between mid-sync of input and start black set-up yd3 to yd0 = 1011; note 4; see fig.5 - 8.8 -m s v os offset voltage y black to re-inserted black see fig.5 -- 10 mv g v voltage gain from y/cvbs i to y o 1.35 1.43 1.50 from y/cvbs i to y o macp = 1 or hd = 1 1.08 1.14 1.20 uv outputs ( pins 14 and 13); note 6 v o(p-p) u output voltage (peak-to-peak value) - 1.33 1.90 v v o(p-p) v output voltage (peak-to-peak value) - 1.05 1.50 v z o output impedance (both outputs) -- 250 w v o dc output voltage level 2.3 2.6 2.9 v g v voltage gain from u in to u out 0.94 0.97 1.00 from v in to v out 0.94 0.97 1.00 g eneral v diff difference between black levels of yuv outputs in rgb mode and yuv mode sync locked mixed rgb/yuv via fast blanking -- 10 mv nl non-linearity any input to any output -- 5% b bandwidth at - 3 db any input to any output; c l =15pf 7 -- mhz a c crosstalk between rgb and uv in signals on uv out f=0to5mhz --- 50 db b bandwidth at - 1 db any input to any output; c l =15pf 5 -- mhz t clamp internal y clamping time constant - 10 - ms f ast switch f( pin 18) v il low level input voltage uv switched on 0 - 0.5 v v ih high level input voltage rgb switched on 0.9 - 3.0 v t d switching delay between f and yuv -- 20 ns symbol parameter conditions min. typ. max. unit
1996 jan 17 29 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 e xternal clamp input ( pin 17) v il low level input voltage (pin clp) no clamping 0 - 0.6 v v ih high level input voltage (pin clp) clamping 2.4 - 5.5 v t w(clamp) clamping pulse width note 7 1.8 3.5 -m s v os(clamp) clamping offset voltage on uv outputs -- 10 mv z i input impedance ecl = 1 3 -- m w colour matrix g v voltage gain from r to y out 0.41 0.43 0.45 from g to y out 0.80 0.84 0.88 from b to y out 0.15 0.16 0.17 from r to u out 0.41 0.43 0.45 from g to u out 0.80 0.84 0.88 from b to u out 1.21 1.27 1.33 from r to v out 0.95 1.00 1.05 from g to v out 0.80 0.84 0.88 from b to v out 0.15 0.16 0.17 output and in/output port o port ( pin 16); opb/clp mode v oh high level output voltage 4.0 5 5.5 v v ol low level output voltage - 0.2 0.4 v i sink sink current 100 --m a i source source current 100 --m a i/o port ; opb/clp mode v oh high level output voltage -- v cc v v ol low level output voltage - 0.2 0.4 v i sink sink current 2 -- ma v ih high level input voltage 2.0 -- v v il low level input voltage -- 0.6 v symbol parameter conditions min. typ. max. unit
1996 jan 17 30 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 notes to the characteristics 1. all frequency variations are referred to 3.58 mhz or 4.43 mhz carrier frequency. all oscillator specifications are measured with the philips crystal series 9920 520 0047x and 9920 520 0048x. the oscillator circuit is insensitive to the spurious responses of the crystal. the typical crystal parameters for the crystals mentioned above are: a) load resonance frequency f 0 = 4.433619 mhz or 3.579545 mhz (c l = 20 pf). b) motional capacitance c m = 20.6 f f (4.43 mhz crystal) or 14.7 f f (3.58 mhz crystal). c) parallel capacitance c 0 = 5 pf for both crystals. d) the minimum detuning range can only be specified if both the ic and the crystal tolerances are known and the general specifications given for the subcarrier regeneration are therefore valid for the specified crystal series. in the figure tolerances of the crystal with respect to nominal frequency, motional capacitance and ageing have been taken into account and have been counted for by gaussian addition. whenever different typical crystal parameters are used, the following equation might be helpful for calculating the impact on the detuning capabilities: e) detuning range proportional to: f) the resulting detuning range should be corrected for temperature shift and supply deviation of both the ic and the crystal. for the above mentioned crystals, the actual load capacitance in the application should be c l =18pf to account for parasitic capacitance on and off chip. for 3-norm applications with two crystals connected to one pin, the maximum load capacitance of the crystal pin should not exceed 12 pf. 2. yd3 and yd2 are equal significant bits, both representing a 160 ns delay step. yd1 represents 80 ns and yd0 represents a 40 ns delay step. 3. the hue control is active for ntsc on the - (r - y) and - (b - y) signals and for palplus only on the demodulated helper signal. 4. this delay is partially caused by the low-pass filter at the sync separator input. 5. the delay between the positive edge of va and the first negative edge of ha (or positive edge of clp) after va is 34.5 m s for field 1 and 2.5 m s for field 2 (17 llc pulses with or without respectively). especially for palplus signals the regenerated va pulses must have a fixed and known phase relation to the undisturbed v pulses of the incoming video signal. this relation must remain correct as long as the vertical divider is in norm mode (indirect sync mode), so the coincidence window used here must be a half line compared to the one line coincidence window used outside palplus. with a well defined phase relation of the regenerated va pulses to the regenerated ha pulses a correct field identification (odd/even) and all the required timing signals referring to a certain line in each frame can be generated externally in the palplus decoder environment. 6. the output signals of the demodulator are called - (r - y) and - (b - y) in this specification. the colour difference input and output signals of the yuv switch are called uv signals. however, these signals do not have the amplitude correction factor of real uv signals. they are called uv signals and not - (r - y) and - (b - y) to prevent confusion between the colour difference signals of the demodulator and the colour difference signals of the yuv switch. 7. the maximum external clamping pulse width is the minimum available blanking level time of the supplied rgb signals. c m 1 c o c l ------- - + ? ? ?? 2 --------------------------- 1 2f h --------------
1996 jan 17 31 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 test and application information handbook, full pagewidth mbg901 82 k w 15 k w 240 w 120 k w 100 w 100 w 100 m f 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf 3.3 nf 100 nf 100 nf 18 pf 18 pf 100 nf 470 nf 3.3 nf 1nf 100 nf 75 w 75 w 100 nf 75 w 100 nf 75 w 100 nf 75 w 100 nf 75 w 100 nf 16 15 14 13 12 11 10 9 12 3 45678 14 13 12 11 10 9 8 12 34 56 7 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 12345678910111213141516 TDA9144 tda4665 pc74hcu04 5v1 llc interface to tda9151 5 v 8 v gnd y/cvbs c fscomb addr (cvbs) r g b f clp/ha scl sda sc va y out v out u out i/o port o port/llc lcc ha fig.10 application circuit. pins 28 and 32 are sensitive to leakage currents. keep the analog and digital ground currents well separated the decoupling capacitor between pin 8 and 9 must be placed as close to the ic as possible.
1996 jan 17 32 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 equivalent pin circuits pin symbol equivalent pin circuit 1 - (r - y) 2 - (b - y) 3u in 100 w 1 0.2 ma mge046 100 w 2 0.2 ma mge047 3 0.07 ma 100 w mge048
1996 jan 17 33 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 4v in 5 scl 6 sda 7v cc 8 dec pin symbol equivalent pin circuit 4 100 w dct clin 0.07 ma mge049 5 mge050 6 data mge051 7 mge052 8 5 v mge053
1996 jan 17 34 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 9 dgnd 10 sc 11 va 12 y out pin symbol equivalent pin circuit 9 mge054 10 mge055 11 mge056 100 w 12 0.5 ma mge057
1996 jan 17 35 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 13 v out 14 u out 15 i/o port 16 o port/llc pin symbol equivalent pin circuit 100 w 13 0.5 ma mge058 100 w 14 0.5 ma mge059 15 mge060 16 100 w mge061
1996 jan 17 36 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 17 clp/ha 18 f 19 b 20 g 21 r pin symbol equivalent pin circuit 17 mge062 18 100 w mge064 19 100 w 20 100 w 21 100 w clp 0 to 60 m a 0 to 60 m a 0 to 60 m a mge063
1996 jan 17 37 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 22 addr (cvbs) 23 fscomb 24 hpll 25 c pin symbol equivalent pin circuit 22 100 w 0.5 ma mge065 23 100 w mge066 24 4 v 4 v mge067 25 100 w 1 m w mge068
1996 jan 17 38 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 26 y/cvbs 27 agnd analog ground 28 filt ref 29 cpll pin symbol equivalent pin circuit 26 1 k w 100 w 3.5 m a mge069 28 init 4 v mge071 29 mge072
1996 jan 17 39 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 30 xtal 31 xtal2 32 sec ref pin symbol equivalent pin circuit 30 1 k w 0.2 ma mge073 31 1 k w 0.2 ma mge074 32 cal mge075
1996 jan 17 40 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 package outline unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot232-1 92-11-17 95-02-04 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 29.4 28.5 9.1 8.7 3.2 2.8 0.18 1.778 10.16 10.7 10.2 12.2 10.5 1.6 4.7 0.51 3.8 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 32 1 17 16 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z a max. 12 a min. a max. sdip32: plastic shrink dual in-line package; 32 leads (400 mil) sot232-1
1996 jan 17 41 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). soldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. repairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1996 jan 17 42 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 notes
1996 jan 17 43 philips semiconductors preliminary speci?cation i 2 c-bus controlled, alignment-free pal/ntsc/secam decoder/sync processor with palplus helper demodulator TDA9144 notes
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(63) 2 816 6380, fax. (63) 2 817 3474 portugal: philips portuguesa, s.a., rua dr. antnio loureiro borges 5, arquiparque - miraflores, apartado 300, 2795 linda-a-velha, tel. (01)4163160/4163333, fax. (01)4163174/4163366 singapore: lorong 1, toa payoh, singapore 1231, tel. (65)350 2000, fax. (65)251 6500 south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430, johannesburg 2000, tel. (011)470-5911, fax. (011)470-5494 spain: balmes 22, 08007 barcelona, tel. (03)301 6312, fax. (03)301 42 43 sweden: kottbygatan 7, akalla. s-164 85 stockholm, tel. (0)8-632 2000, fax. (0)8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01)488 2211, fax. (01)481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1. taipeh, taiwan roc, p.o. box 22978, taipei 100, tel. (886) 2 382 4443, fax. (886) 2 382 4444 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, thailand, tel. (66) 2 745-4090, fax. (66) 2 398-0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0 212)279 27 70, fax. (0212)282 67 07 ukraine: philips ukraine, 2a akademika koroleva str., office 165, 252148 kiev, tel. 380-44-4760297, fax. 380-44-4766991 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. (0181)730-5000, fax. (0181)754-8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 internet: http://www.semiconductors.philips.com/ps/ for all other countries apply to: philips semiconductors, international marketing and sales, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-2724825 scds47 ? philips electronics n.v. 1996 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 537021/1100/01/pp44 date of release: 1996 jan 17 document order number: 9397 750 00577

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